Network and edge acceleration tile (NEXT) architecture

US11983131B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Patrick G. Kutch · Tigard, US
• Andrey Chilikin · Limerick, IE
• Niall D. McDonnell · Limerick, IE
• Brian Andrew Keating · Shannon, IE
• Naveen Lakkakula · Chandler, US
• Ilango S. Ganga · Cupertino, US
• Venkidesh Krishna Iyer · Chandler, US
• Patrick Fleming · Pine Island, US
• Lokpraveen Mosur · Worcester, US

Key dates

• Filing date: Dec 26, 2020
• Grant date: May 14, 2024
• Expiry date: Nov 5, 2041

Classification

• Technology area (CPC —): General

Abstract

Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.