Semiconductor testing structure and method for forming same
US11984370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2021 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Feb 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor testing structure forming method includes: a semiconductor substrate is provided, and the semiconductor substrate includes a plurality of active areas arranged separately; a first conductive wire is formed at a preset distance from the plurality of active areas in the semiconductor substrate, and the first conductive wire is connected with a substrate of a respective active device formed in each of the plurality of active areas; a plurality of first contact holes is formed on the first conductive wire; and a first metal layer is formed on top of each of the plurality of first contact holes to obtain the semiconductor testing structure, where the first metal layer is electrically connected with a first common pad and the first common pad is configured to perform an electric performance test on the semiconductor testing structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.