Array substrate, display panel and electronic device
US11984453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2021 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Mar 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.