Active DC bus voltage balancing circuit
US11984829B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2021 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Mar 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02P2201/03
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A system has a DC bus circuit with first and second terminals, an intermediate node, first and second capacitors, first and second depletion mode FETs, and first and second switching control circuits, where the first depletion mode FET has a drain coupled to the first bus terminal, a source, and a gate coupled to the intermediate node, the second depletion mode FET has a drain coupled to the intermediate node, a source, and a gate coupled to the second bus terminal, the first switching control circuit turns the first depletion mode FET off responsive to a first capacitor voltage of the first bus capacitor being less than or equal to a second capacitor voltage of the second bus capacitor, and the second switching control circuit turns the second depletion mode FET off responsive to the first capacitor voltage being greater than or equal to the second capacitor voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.