Standby voltage condition for fast RF amplifier bias recovery
US11984852B2 · kind B2 · utility
1Cited by
2References
25Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 5, 2023 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Jun 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/453
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.