Chopper amplifying circuit employing negative impedance compensation technique
US11984859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2019 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | May 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45084
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A chopper amplifying circuit employing a negative impedance compensation technique, including a differential input end, a first-level chopper switch, a first-level amplifying circuit, a second-level chopper switch, a second-level amplifying circuit, a negative impedance converting circuit, a negative feedback unit, an input capacitor, and a differential output end, is provided. The differential input end is connected to the first-level chopper switch. An output terminal of the first-level chopper switch is connected to the first-level amplifying circuit through the input capacitor. The first-level amplifying circuit is connected to the second-level chopper switch, which is connected to the second-level amplifying circuit. The second-level amplifying circuit is connected to the differential output end, and is also connected to a feedback input end of the first-level amplifying circuit through the negative feedback unit. The negative impedance converting circuit is parallel-connected to a signal input end of the first-level amplifying circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.