Techniques for mapping coded bits to different channel reliability levels for low density parity check codes
US11984979B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2023 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Jan 17, 2043 |
Classification
- Technology area (CPC —)General
Abstract
Methods, systems, and devices for wireless communications are described. In some examples, a transmitting device may generate a parity check matrix based on performing a lifting operation on a base matrix. Each column of the base matrix may correspond to a different variable node and each row may correspond to a different check node. The transmitting device may then generate a set of coded bits based on the parity check matrix and each coded bit of the set of coded bits may be associated with a respective variable node. Further, the transmitting device may interleave the set of coded bits such that subsets of the set of coded bits associated with a same variable node are mapped to a same channel reliability level and transmit the set of coded bits according to the interleaving.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.