Method for manufacturing bit line structure, method for manufacturing semiconductor structure, and semiconductor structure
US11985814B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2021 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Apr 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0234
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a bit line structure includes the following operations. A bit line conductive layer is formed on a surface of a semiconductor substrate, and the bit line conductive layer is partially located in a groove in the surface of the semiconductor substrate. A first protective layer is formed on surfaces of the bit line conductive layer and the semiconductor substrate. A first barrier layer is formed on a surface of the first protective layer. The surface of the first barrier layer is subjected with passivating treatment. A sacrificial layer is formed on the surface of the first barrier layer, and is provided with a filling part filled in the groove. A part, other than the filling part, of the sacrificial layer is cleaned and stripped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.