Semiconductor memory device having memory layer extending between insulation layer and semiconductor layer
US11985834B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2021 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Mar 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
A semiconductor memory device, includes: a stack including a wiring layer and an insulation layer alternately stacked in a first direction; a semiconductor layer including a first region overlapping with the insulation layer in a second direction, and a second region overlapping with the wiring layer in the second direction; an insulation region between the wiring layer and the second region; and a memory region on the opposite side of the second region from the wiring layer. The wiring layer is farther from the first region in the second direction than the insulation layer is. The second region has a part between the insulation layers in the first direction and protruding further toward the wiring layer than the first region in the second direction. The memory region has a face opposite to the second region and closer to the wiring layer in the second direction than the first region is.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.