Patterning a conductive deposited layer using a nucleation inhibiting coating and an underlying metallic coating
US11985841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2021 |
| Grant date | May 14, 2024 |
| Priority date | — |
| Expiry date | Dec 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/876
Abstract
A semiconductor device having a plurality of layers deposited on a substrate and extending in a first portion and a second portion of at least one lateral aspect defined by a lateral axis thereof, comprises an orientation layer comprising an orientation material, disposed on a first exposed layer surface of the device in at least the first portion; at least one patterning layer comprising a patterning material, disposed on a first exposed layer surface of the orientation layer; and at least one deposited layer comprising a deposited material, disposed on a second exposed layer surface of the device in the second portion; wherein the first portion is substantially devoid of a closed coating of the deposited material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.