Maximum current suppression for power management in a multi-core system
US11989077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2022 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Aug 11, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.