Tiling of cross-resonance gates for quantum circuits
US11989621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2021 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | May 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques regarding tiling a CR gate configuration to one or more lattices characterizing quantum circuit topologies are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tiling component that can generate a cross-resonance gate configuration that delineates a control qubit assignment and a target qubit assignment in conjunction with a frequency allocation onto a lattice characterizing a quantum circuit topology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.