Operation methods for ovonic threshold selector, memory device and memory array
US11990182B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 18, 2022 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Aug 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation method for a memory device is provided. The memory device includes a two-terminal selector and a resistance variable storage element coupled to the two-terminal selector. The method includes providing a voltage pulse to the memory device. A voltage applied across the two-terminal selector during a falling part of the voltage pulse falls below a holding voltage of the two-terminal selector. A voltage falling rate of the falling part at which the voltage applied across the two-terminal selector reaches the holding voltage is raised for reducing threshold voltage drift of the two-terminal selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.