Field Programmable Gate Array system
US11990904B1 · kind B1 · utility
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4References
20Claims
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Key dates
| Filing date | Dec 20, 2023 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Dec 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1774
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Field Programmable Gate Array (FPGA) system includes a main FPGA and one or more sub-FPGAs connected to the main FPGA. The main FPGA is configured to detect a positive edge of a pulse included in a user clock using a sampling clock of the main FPGA, generate a flag using the detected positive edge, generate a clock packet indicating the generated flag, and provide the generated clock packet to any one of the one or more sub-FPGAs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.