Low power retention flip-flop
US11990909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2022 |
| Grant date | May 21, 2024 |
| Priority date | — |
| Expiry date | Mar 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A retention flip-flop includes a master latch outputting a first signal which is generated based on a signal inputted through an input terminal based on first control signals; a slave latch outputting a second signal generated based on the first signal based on the first control signals and second control signals; and a control logic that generates the first control signals based on a clock signal and provides the first control signals to the master latch and the slave latch, and generates the second control signals based on a power down signal and provides the second control signals to the slave latch. The slave latch comprises a retention latch which transmits the first signal to an output terminal as the second signal by operating as an open loop based on the second control signals or maintains the second signal by forming a closed loop based on the second control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.