Adaptive prefetcher for shared system cache
US11994993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2022 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | May 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adaptive prefetcher for a shared system cache of a processing system including multiple requestors having a cache miss monitor and a prefetch controller. The cache miss monitor monitors requests for information from memory and identifies one of the requestors for which an identified cache line is requested. The prefetch controller submits an adaptive request for a subsequent cache line. The subsequent cache line may be determined based on a latency comparison between a loop latency (LL) of the prefetch controller and a stream latency (SL) of the identified requestor. A latency memory may be included that stores stream latencies for the requestors. The latency comparison may be used to determine how many cache lines to skip relative to the identified cache line, such as according to SL*SK<LL≤SL*(SK+1) in which SK is the number of cache lines to skip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.