Register allocation heuristics order
US11995421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2022 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Aug 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4552
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Compilation is supported and improved by varying the order of invocation of register allocation heuristics during code generation. A particular invocation order may be chosen based on one or more compilation scenario properties, such as a target processor architecture, a target operating system, a kind of source code being compiled, or optimization targets for the compiler or the generated code, or a mix thereof. Suitable heuristics invocation orders may be produced efficiently and effectively using a genetic algorithm that is adapted to make a population of invocation orders, select parents, create offspring, and assess invocation order fitness, until the population converges on optimal orders. Invocation order fitness assessments may be based on actual performance or simulated performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.