Lossless tiling in convolution networks—tiling configuration for a sequence of sections of a graph

US11995529B2 · kind B2 · utility

Assignee

• SambaNova Systems, Inc. · US

Inventors

• Tejas Nagendra Babu Nama · Sunnyvale, US
• Ruddhi Chaphekar · Santa Clara, US
• Ram Sivaramakrishnan · San Jose, US
• Raghu Prabhakar · San Jose, US
• Sumti Jairath · Santa Clara, US
• Junjue Wang · San Mateo, US
• Kaizhao Liang · Palo Alto, US
• Adi Fuchs · Princeton Colonial Park, US
• Matheen Musaddiq · Austin, US
• Arvind Krishna Sujeeth · San Francisco, US

Key dates

• Filing date: Jun 30, 2021
• Grant date: May 28, 2024
• Expiry date: Apr 30, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/082
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed is a data processing system that includes compile time logic to section a graph into a sequence of sections including a first section and a second section. The compile time logic is to configure the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section, and configure the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section. The data processing system further includes runtime logic configured with the compile time logic to execute the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations, and execute the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations.