Display driving circuit, display device including the same, and method of operating the same
US11996065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2022 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Nov 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.