Nonvolatile memory cell, nonvolatile memory cell array, and information writing method of nonvolatile memory cell array
US11996130B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Jun 11, 2020 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Dec 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory cell includes a resistance-change nonvolatile memory element 50 and a selection transistor TR. One end of the nonvolatile memory element 50 is connected to one source/drain region 15A of the selection transistor TR and is connected to a write line WR. The other source/drain region 15B of the selection transistor TR is connected to a select line SL. The other end of the nonvolatile memory element 50 is connected to a bit line BL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.