Memory chip and operating method thereof
US11996165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2022 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Sep 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.