Semiconductor structure and method for forming the same
US11996321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2021 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Feb 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a conductive feature through a first dielectric layer, sequentially forming a second dielectric layer and a third dielectric layer over the first dielectric layer, and etching the third dielectric layer to form an opening. A first width of the opening at a top surface of the third dielectric layer is greater than a second width of the opening at a first interface between the third dielectric layer and the second dielectric layer. The method also includes etching the second dielectric layer until the opening extends to the conductive feature, thereby forming an enlarged opening, and forming a metal material in the enlarged opening. A third width of the enlarged opening at the first interface is equal to or less than a fourth width of the enlarged opening at a second interface between the second dielectric layer and the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.