Timing sequence generation circuit
US11996849B2 · kind B2 · utility
1Cited by
18References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2023 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Mar 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0996
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.