Correcting memory data using an error code and a memory test result
US11996859B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2020 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Dec 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder is disclosed with error correction for memory data. The decoder's error correction is extended to additional faulty bits by integrating a memory test into the error correction to identify faulty bits in the memory data. A method for correction can include writing a known pattern to the failing address (and possibly to neighboring addresses), reading the known pattern back and comparing the read data to the written pattern to identify the failing bits. The failing bits are then used together with the error correction data to correct memory data having multiple incorrect bits or to alert other components about the failing bit locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.