Method for manufacturing semiconductor structure and semiconductor structure
US11997845B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2021 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | Oct 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
Abstract
A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate is provided with a peripheral area and an array area; an insulation layer is formed on the substrate; a first mask layer with a first mask pattern is formed on the insulation layer; the insulation layer is etched by taking the first mask layer as a mask, to form a contact hole in the array area; a first electrode layer is formed; a second mask layer with a second mask pattern is formed, in which the second mask layer is arranged on the first electrode layer; and the first electrode layer and the first mask layer are etched by taking the second mask layer as a mask until the insulation layer in the array area is exposed, in which a remaining portion of the first electrode layer forms a lower electrode layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.