Array substrate and display panel
US11997877B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Aug 26, 2020 |
| Grant date | May 28, 2024 |
| Priority date | — |
| Expiry date | May 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/124
Abstract
An array substrate and a display panel are provided. A driving circuit layer of the array substrate includes a low temperature polysilicon thin film transistor and a low temperature polycrystalline oxide thin film transistor which are electrically connected with each other. A hydrogen blocking layer is formed on at least one of an upper side and a lower side of an oxide active layer of the low temperature polysilicon thin film transistor. The hydrogen blocking layer can block hydrogen ions in other film layers to invade the oxide active layer and avoid that device characteristics are drifted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.