Integrated circuit including test circuit and method of manufacturing the same
US12000888B2 · kind B2 · utility
0Cited by
6References
18Claims
0Family size
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Key dates
| Filing date | Jul 5, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Aug 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318513
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit includes first to nth metal layers vertically stacked on a substrate, and a test circuit outputting a test result signal according to a characteristic of each of the first to nth metal layers. The test circuit includes first to nth test circuits for generating a plurality of clock signals. Each clock signal of the plurality of clock signal has a frequency according to a characteristic of a corresponding metal layer among the first to nth metal layers, and n is a natural number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.