System and method for storage class memory tiering
US12001329B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2021 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Jan 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device defines portions of the storage space as memory mode memory or storage mode memory. Memory mode memory is represented as a portion of a system physical address space of an information handling system, and storage mode memory is represented as a storage device in the information handling system. An operating system instantiates a paged virtual memory architecture on the information handling system. The information handling system determines a page miss rate for pages stored in the first portion of the storage space, receives a request to increase a first size of the first portion of storage space in response to determining the page miss rate, and increases the first size of the first portion of storage space to a second size in response to the request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.