Memory device, memory system including the same, and operating method of the memory system
US12001683B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Dec 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device including a memory cell array, a first latch, a plurality of program latches, and a second latch and a memory controller configured to provide a command to the memory device. The memory device may sense first data from a first region of the memory cell array, store the sensed first data in the first latch, transfer the sensed first data to the second latch, output the first data from the second latch to the memory controller, and transfer the first data from the second latch to a first program latch of the plurality of program latches, in response to a first read command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.