Lossless tiling in convolution networks—graph metadata generation
US12001936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Nov 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing graph of an application with a sequence of processing nodes is obtained which processes an input and generates an intermediate representation a further intermediate representation, and an output representation of the input at stages in the sequence of processing nodes. Graph metadata is generated that specifies a non-overlapping target tiling configuration for the output representation, an overlapping tiling configuration for the input, an overlapping tiling configuration for the intermediate representation, and a third tiling configuration for the further intermediate representation. The processing graph is modified based on the graph metadata to conform to the parameters specified by the graph metadata. A set of computer instructions is then created to execute the modified processing graph on a target processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.