Gate driver on array circuit and display panel
US12002434B2 · kind B2 · utility
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1References
20Claims
0Family size
Inventor
Key dates
| Filing date | Aug 18, 2021 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Aug 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present embodiment provides a GOA circuit and a display panel, in which the GOA circuit comprises a forward/backward scanning control module, an output module, a potential regulation module, a node control module, and a voltage stabilizer module. A first node and a third node are not conducted when a second node is at a second potential; the first node and the third node are conducted and have a second potential when the second node is at a third potential, wherein the second potential is opposite to the third potential. Thus, GOA circuit's leakage issue existing in the TP suspension stage can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.