Memory circuit and memory
US12002503B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Dec 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a memory circuit and a memory. The memory circuit at least includes a plurality of memory blocks. Each of the memory blocks includes a first memory sub-block, a second memory sub-block, and a third memory sub-block arranged in sequence; the second memory sub-block includes a first memory unit and a second memory unit; the first memory sub-block and the first memory unit are configured to store high-order bytes; the second memory unit and the third memory sub-block are configured to store low-order bytes; and in an arrangement direction of memory sub-blocks, different memory units that are arranged side by side have different block selection addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.