Write circuit of memory device and method of operating the same
US12002542B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Dec 2, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Dec 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.