Method of manufacturing a III-N enhancement mode HEMT device
US12002680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2021 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Apr 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.