Barrier structures for underfill containment

US12002727B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ziyin Lin · Chandler, US
• Vipul V. Mehta · Chandler, US
• Wei Li · Shanghai, CN
• Edvin Cetegen · Chandler, US
• Xavier Francois Brun · Hillsboro, US
• Yang Guo · Nanhu, CN
• Soud Choudhury · Chandler, US
• Shan Zhong · Clarksville, US
• Christopher L. Rumer · Chandler, US
• Nai-Yuan Liu · Chandler, US
• Ifeanyi Okafor · Chandler, US
• Hsin-Wei Wang · Chandler, US

Key dates

• Filing date: Feb 11, 2020
• Grant date: Jun 4, 2024
• Expiry date: Jul 19, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/35121
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.