Semiconductor protection device
US12002890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Nov 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.