Diode and method of making the same
US12002891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Sep 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with <100> orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with <100> orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary. Next is annealing the respective first and second cleaned wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers, followed by bonding together respective first and second heat-treated wafers to yield a mated and/or bonded four-layer substrate having a first heavy doped n-type layer, a second gradient doped n-type layer, a third gradient doped p-…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.