Controlling duty cycle distortion with a mixed-signal circuit
US12003241B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Controlling Duty Cycle Distortion with a Mixed-Signal Circuit A method controls the duty cycle distortion of clock signals. An electronic device obtains an input clock signal and generates a first output voltage and a second output voltage from the input clock signal. The first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal. The second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal. The difference between the first and second DC voltage levels corresponds to the duty cycle distortion level of the input clock signal. A duty cycle control signal is generated based on the difference between the first and second DC voltage levels to control the high voltage duty cycles of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.