Techniques, devices, and instruction set architecture for balanced and secure ladder computations
US12003633B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Mar 29, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Aug 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed are apparatuses, systems, and techniques to perform and facilitate secure ladder computational operations whose iterative execution depends on secret values associated with input data. Disclosed embodiments balance execution of various iterations in a way that is balanced for different secret values, significantly reducing vulnerability of ladder computations to adversarial side-channel attacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.