Three-dimensional semiconductor memory devices
US12004350B2 · kind B2 · utility
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24References
20Claims
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Key dates
| Filing date | Aug 12, 2022 |
| Grant date | Jun 4, 2024 |
| Priority date | — |
| Expiry date | Aug 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/696
Abstract
A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.