Patent · US Active

Method and system for testing an integrated circuit

US12007438B2 · kind B2 · utility

0Cited by

8References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Chi-Che Wu · Taipei, TW
Tsung-Yang Hung · Dashulong, TW
Ming-Yih Wang · Jinshanmian, TW

Key dates

Filing date	Feb 9, 2023
Grant date	Jun 11, 2024
Priority date	—
Expiry date	Feb 9, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2834
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method is provided and includes several operations: testing multiple scan chains in multiple shift cycles to obtain multiple values; determining at least one fail chain in the scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the values; mapping the at least one fail chain and the at least one fail shift cycle to the scan chains to identify the at least one fail flip flop; and identifying at least one fault site corresponding to the at least one fail flip flop.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.