Low-latency optical connection for CXL for a server CPU
US12007929B2 · kind B2 · utility
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Key dates
| Filing date | Oct 9, 2020 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Jul 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.