Circuit carrier
US12008205B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2023 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Jun 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2203/04111
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit carrier includes a substrate, a capacitive electrode layer, a plurality of metal pads and a plurality of bridges, and a plurality of conductive pillars. The capacitive electrode layer formed on a surface of the substrate and includes a plurality of first electrodes and a plurality of second electrodes. At least two of the first electrodes are connected to each other and be arranged across a die-bonding region of the substrate for separating at least two of the second electrodes that partially protrude from the die-bonding region to respectively form extensions. The metal pads and the bridges are formed on another surface of the substrate and are located outside of the die-bonding region. Each of the bridges connects two of the metal pads, and each of the conductive pillars is embedded in the substrate and connects one of the extensions and a corresponding one of metal pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.