Semiconductor device
US12009310B2 · kind B2 · utility
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14Claims
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Assignee
Inventor
Key dates
| Filing date | Dec 29, 2021 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Dec 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A conductive plate includes a first slit formed in the space between a first chip area and a second chip area, a second slit formed in the space between the first chip area and a terminal area, and a third slit formed in the space between the second chip area and the terminal area. The first slit is a continuous line that penetrates through the conductive plate, whereas the second and third slits are continuous lines that do not penetrate through the conductive plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.