Flip-flop circuit, semiconductor integrated circuit device, and vehicle
US12009817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2022 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Aug 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit includes master latch including a first inverter and a first tri-state inverter, wherein the first tri-state inverter includes a first NMOS transistor and a first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter, wherein the second tri-state inverter includes a second PMOS transistor and a second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.