Decision feedback equalizer circuit
US12009950B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 4, 2021 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Feb 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03006
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a decision feedback equalizer circuit. The decision feedback equalizer circuit includes: a first adder circuit, configured to add sampled data, first correction data and target correction data; a first sampler amplifier, configured to sample data output by the first adder circuit through a first signal component in a first clock signal to obtain a first sampling result; a second adder circuit, configured to add the sampled data, the first correction data and the target correction data; a second sampler amplifier, configured to sample data output by the second adder circuit through a second signal component in the first clock signal to obtain a second sampling result; and a correction parameter processing element, configured to determine the target correction data through a second clock signal, the first sampling result and the second sampling result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.