Efficient parallelized computation of a Benes network configuration
US12010042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2019 |
| Grant date | Jun 11, 2024 |
| Priority date | — |
| Expiry date | Feb 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/1515
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A routing controller (30) includes an interface (68) and multiple processors (60) The interface is configured to receive a permutation (76) defining requested interconnections between N input ports and N output ports of a Benes network (24). The Benes network includes multiple 2-by-2 switches (42), and is reducible in a plurality of nested subnetworks associated with respective nesting levels, down to irreducible subnetworks including a single 2-by-2 switch. The multiple processors are configured to collectively determine a setting of the 2-by-2 switches that implements the received permutation, including determining sub-settings for two or more subnetworks of a given nesting level in parallel, and to configure the multiple 2-by-2 switches of the Benes network in accordance with the determined setting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.