Patent · US Active

Memory-efficient hardware cryptographic engine

US12010209B2 · kind B2 · utility

0Cited by

2References

19Claims

0Family size

Assignee

Nordic Semiconductor ASA · NO

Inventors

Marko Winblad · Trondheim, NO
Markku Vähätaini · Trondheim, NO
James NEVALA · Trondheim, NO
Matti Tiikkainen · Trondheim, NO
Hannu Talvitie · Oulu, FI

Key dates

Filing date	May 29, 2019
Grant date	Jun 11, 2024
Priority date	—
Expiry date	Apr 14, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A hardware cryptographic engine comprises a direct-memory-access (DMA) input module for receiving input data over a memory bus, and a cryptographic module. The cryptographic module comprises an input register having an input-register length, and circuitry configured to perform a cryptographic operation on data in the input register. The hardware cryptographic engine further comprises an input-alignment buffer having a length that is less than twice said input-register length, and alignment circuitry performing an alignment operation on input data in the input-alignment buffer. The hardware cryptographic engine is configured to pass input data, received by the DMA input module, from the memory bus to the input register of the cryptographic module after buffering an amount of input data no greater than the length of the input-alignment buffer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.