Communicating faults to an isolated safety region of a system on a chip
US12012125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2021 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Dec 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07C5/008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various examples, an integrated circuit includes first and second portions. The first portion includes a timer that starts when the first portion transmits at least one error signal to the second portion. The timer may reset when data corresponding to at least one fault has been cleared from the first portion. The first portion transmits a timeout error signal when the timer indicates at least a predetermined amount of time has elapsed. The second portion receives the at least one error signal and the timeout error signal when the timeout error signal has been sent. The second portion may notify an external system after the timeout error signal is received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.