Instruction execution method and instruction execution device
US12014181B2 · kind B2 · utility
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4References
18Claims
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Key dates
| Filing date | Nov 4, 2022 |
| Grant date | Jun 18, 2024 |
| Priority date | — |
| Expiry date | Nov 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3818
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction configuration and execution method includes the following steps. A target instruction is received through an instruction cache. The target instruction is decoded by an instruction translator. It is determined whether the target instruction has the authority to read or write the model specific register in an unprivileged state. It is determined whether the model specific register index of the specific instruction corresponds to a specific model specific register, so as to order the microprocessor to perform an instruction serialization operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.